This invention relates to digital signal processing circuitry in which timing information is propagated with the processed signals and in particular to a method of implementing such circuitry in field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs).
Typically, special purpose digital signal processing circuitry is designed using either FPGAs or ASICs. The design methodology for these types of circuits is similar. The user specifies the operation of the circuit functionally, debugs the functional representation and then has the functional representation converted automatically or semi-automatically into a hardware implementation. The designer then massages the automatically generated hardware implementation to produce a circuit design which performs the desired function.
The circuitry in an ASIC is a combination of interconnected macrocells. Each macrocell represents a circuit element which may include multiple electronic components (e.g. transistors, resistors, capacitors). In addition, macrocells may be defined hierarchically so that multiple primitive macrocells may be combined to form a more complex macrocell. Once the design for an ASIC has been generated, it is converted into an actual circuit through a process that implements the individual components of each of the macrocells in the design as a single integrated circuit. Once an ASIC has been made, it is not possible to reconfigure its macrocells.
A circuit implemented in an FPGA, on the other hand, is designed by specifying interconnection of macrocells which may be formed from the gates on the gate array. A design implemented in an FPGA does not need to be specially fabricated, but may be simply programmed into the FPGA at power up using a serial programmable read only memory (PROM) or using a control interface such as that specified by the joint test action group (JTAG). The design in an FPGA may also change partially or fully during the course of an application. This is referred to as "reconfigurable logic" in the literature.
Digital designs implemented in ASICs, FPGAs and even random logic are prone to timing errors or time delays. These errors typically occur when a signal processed by one part of the circuit is combined with a signal processed by another part of the circuit. Due to timing differences on the input signals or propagation delays through the respective signal processing circuitry, the signals may not be properly aligned at the point in the circuit at which they are to be combined. These timing problems are typically resolved by inserting compensating delays at various locations in the circuitry such that the signals have the desired timing relationship when they are combined.
In U.S. Pat. No. 5,561,617 entitled PYRAMID PROCESSOR INTEGRATED CIRCUIT, an ASIC is described which propagates timing signals in parallel with the signal processing circuitry with delay adjustments to match the delay of the timing signals to the processing delays of the signal processing circuitry. The system described in this patent is a video signal processing system and the timing signals which are propagated with the video signals are the horizontal active (HA) and vertical active (VA) signals. These signals define times at which data representing active picture elements (pixels) are present in the video input and output signals. Active pixels are those which produce image information on a display device. By providing appropriately delayed timing signals along with the output signals, other functions in a system that follow the processor can be independent of the actual timing delay that occurred in the processor to obtain the appropriate results. Other advantages of including timing with the video data signals are: (a) active data only can be stored automatically, (b) control functions such as the length of line delays can be set automatically, (c) active data can be processed differently from non-active data, (d) boundary of image data can be processed differently from active data, (e) the process delay through a function can change as a function of processing parameters without effecting the control of other processing modules, and (f) the time interval between active data, i.e., horizontal blanking, could be variable to adjust for asynchronous data streams. The system described in this patent was implemented using compensating delay elements, having relatively long delay times, to pass the timing signals around complex signal processing circuitry. As a part of the design process, the time used to process the signals through this circuitry was determined, as part of the design process, so that the length of the compensating delay could be determined. Thus, while having the timing signal at the input and output of the ASIC aided in the use of the ASIC to implement more complex signal processing circuitry, there was no saving in design effort for the ASIC itself.